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2big_nas [2013/06/27 17:58]
hanno
2big_nas [2013/07/04 07:57] (current)
hanno
Line 475: Line 475:
   * 4x programmable address windows   * 4x programmable address windows
   * SDRAM and PCIe interface access   * SDRAM and PCIe interface access
-=== Default Address Map ===+=== Default Address Map (p.41) === 
 +^Desc ^Size ^Base ^End ^Num ^State ^ 
 +|SDRAM CS0|256MB|0x0000 0000|0x0FFF FFFF| | | 
 +|SDRAM CS1|256MB|0x1000 0000|0x1FFF FFFF| | | 
 +|SDRAM CS2|256MB|0x2000 0000|0x2FFF FFFF| | | 
 +|SDRAM CS3|256MB|0x3000 0000|0x3FFF FFFF| | | 
 +|reserved| |0x4000 0000|0x7FFF FFFF| | | 
 +|PCIe Memory|512MB|0x8000 0000|0x9FFF FFFF| | | 
 +|PCIe-1 Memory|512MB|0xA000 0000|0xBFFF FFFF|(reserved)|6282 guess| 
 +|PCIe I/O|64KB|0xC000 0000|0xC000 FFFF| | | 
 +|PCIe-1 I/O|64KB|0xC001 0000|0xC001 FFFF|(reserved)|6282 guess| 
 +|reserved| |0xC002 0000|0xC800 FFFF| | | 
 +|Security SRAM|64KB (2KB)|0xC801 0000|0xC801 FFFF| | | 
 +|reserved| |0xC802 0000|0xCFFF FFFF| | | 
 +|Internal Registers|1MB|0xD000 0000|0xD00F FFFF| | | 
 +|reserved| |0xD010 0000|0xD7FF FFFF| | | 
 +|NAND Flash|128MB|0xD800 0000|0xDFFF FFFF| | | 
 +|reserved| |0xE000 0000|0xE7FF FFFF| | | 
 +|SPI Flash|128MB|0xE800 0000|0xEFFF FFFF| | | 
 +|BootROM|128MB|0xF000 0000|0xF7FF FFFF| | | 
 +|Boot device|128MB|0xF800 0000|0xFFFF FFFF| | | 
 +=== LaCie Configured Address Map (mvSysHwConfig.h) ===
 ^Desc ^Size ^Base ^Notes ^Num ^State ^ ^Desc ^Size ^Base ^Notes ^Num ^State ^
 |SDRAM CS0|256MB|0x00000000| | |dis| |SDRAM CS0|256MB|0x00000000| | |dis|
Line 492: Line 513:
 |DEVICE CS3|16M|0xFF000000|Boot device|0xA|dis| |DEVICE CS3|16M|0xFF000000|Boot device|0xA|dis|
  
-* from func. spec. * +Wish found this earlier (kirkwood/cpu.c): Linux expects the internal registers to be at 0xF1000000
-|reserved| |0xA0000000 - 0xBFFFFFFF| +
-|PCIe I/O|64KB|0xC0000000 - 0xC000FFFF| +
-|reserved| |0xC0010000 - 0xC001FFFF| +
-|reserved| |0xC0020000 - 0xC800FFFF| +
-|Security SRAM|64KB (2KB)|0xC8010000 - 0xC801FFFF| +
-|reserved| |0xC8020000 - 0xCFFFFFFF| +
-|Internal Registers|1MB|0xD0000000 - 0xD00FFFFF| +
-|reserved| |0xD0100000 - 0xD7FFFFFF| +
-|NAND Flash|128MB|0xD8000000 - 0xDFFFFFFF| +
-|reserved| |0xE0000000 - 0xE7FFFFFF| +
-|SPI Flash|128MB|0xE8000000 - 0xEFFFFFFF| +
-|BootROM|128MB|0xF0000000 - 0xF7FFFFFF| +
-|Boot device|128MB|0xF8000000 - 0xFFFFFFFF|+
  
-Bloody hell... +Internal registers base address is set in register offset 0x20080 (arch-kirkwood/kirkwood.h): i.e0xF1020080 = 0xF1000000
-  * #undef  INTER_REGS_BASE +
-  * #define INTER_REGS_BASE         0xd0000000 +
-  * #define NAND_FLASH_BASE         0xffff0000 +
-  * #define BOOTER_PAGE_NUM         2 +
-  * #define BOOTER_BASE             0x00020000 + PAGE_SIZE +
-  * #define BOOTER_END          (BOOTER_BASE + (BOOTER_PAGE_NUM * PAGE_SIZE)) +
-  * #define NAND_CMD_PORT       (0x1 << (NFLASH_DEV_WIDTH >> 4)) +
-  * #define NAND_ADDR_PORT      (0x2 << (NFLASH_DEV_WIDTH >> 4)) +
-  * #define NUM_BLOCKS              2048 +
-  * #define PAGES_PER_BLOCK         64 +
-  * #define PAGE_SIZE               2048     /* Bytes */ +
-  * #define SPARE_SIZE              64 +
-  * #define CFG_NAND_PAGE_SIZE      (2048)          /* NAND chip page size          */ +
-  * #define CFG_NAND_BLOCK_SIZE     (128 << 10)     /* NAND chip block size         */ +
-  * #define CFG_NAND_PAGE_COUNT     (64)            /* NAND chip page count         */ +
-  * #define CFG_NAND_BAD_BLOCK_POS  (0)             /* Location of bad block marker */ +
-  * #define CFG_NAND_U_BOOT_OFFS    CFG_MONITOR_BASE        /* Offset to U-Boot image       */ +
-  * #define CFG_NAND_U_BOOT_SIZE    CFG_MONITOR_LEN /* Size of RAM U-Boot image     */ +
-  * #define CFG_NAND_U_BOOT_DST     CFG_MONITOR_IMAGE_DST   /* Load NUB to this addr        */ +
-  * #define CFG_NAND_U_BOOT_START   CFG_NAND_U_BOOT_DST /* Start NUB from this addr */+
  
-= Trying to find ENV in NAND = 
- 
-  I think it uses /* Use the new NAND code. */ in mv_kw.h 
-  And it also #undef CFG_ENV_IS_IN_FLASH which is interesting... 
-  Think only need ENV_SIZE and ENV_OFFSET when in NAND 
- 
-  #define CFG_ENV_OFFSET 0xA0000 (640 << 10) /* environment starts here  */ 
-  #define CFG_ENV_SECT_SIZE 0x20000 (128 << 10) /* environment take 1 block */ 
-  #define CFG_ENV_SIZE 0x20000 (CFG_ENV_SECT_SIZE) /* environment take 1 block */  
-  #define CFG_NBOOT_BASE 0  
-  #define CFG_NBOOT_LEN 0x01000 (4 << 10) /* Reserved 4KB for boot strap */ 
-  #define CFG_MONITOR_LEN 0xA0000 (640 << 10) /* Reserve 4 * 128KB + ENV = 640KB for Monitor */ 
-  #define CFG_MONITOR_BASE 0 
-  #define CFG_MONITOR_IMAGE_OFFSET 0 /* offset of the monitor from the u-boot image */ 
-  #define CFG_MONITOR_IMAGE_DST 0x60000?(TEXT_BASE) /* Load NUB to this addr */ 
-  #define CFG_ENV_ADDR    0xA0000 (CFG_ENV_OFFSET) 
- 
-./tools/doimage -T nand -D 0x06000000 -E 0x6070000 -P 2048 -R dramregs_533ddr3_2big_A.txt u-boot-nas2big-revB-2.0.7.bin u-boot-nas2big-revB-2.0.7-nand.kwb 
2big_nas.1372348694.txt.gz · Last modified: 2013/06/27 17:58 by hanno