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2big_nas [2013/06/13 15:31]
hanno
2big_nas [2013/07/04 07:57] (current)
hanno
Line 395: Line 395:
  
 ^Address ^Part ^Description ^ ^Address ^Part ^Description ^
-|0x3E|Serial ROM or Debug Port||+|0x3E|G762|Fan controller|
 |0x50 - 0x53|HT24LC08|1KB EEPROM| |0x50 - 0x53|HT24LC08|1KB EEPROM|
-|0x64|Debug Port or Serial ROM||+|0x64|Debug Port/Serial ROM ?||
 |0x68|DS1337|RTC| |0x68|DS1337|RTC|
- 
-=== CPU Address Decoding === 
-Sheeva CPU core has 13 address windows: 
-  * 4x for CPU access to DRAM CS 
-  * 1x for CPU access to internal registers 
-  * 8x configurable for CPU access to remaining chip resources 
-== DRAM Windows == 
-  * 8-bit BASE & SIZE registers 
-  * BASE corresponds to address bits [31:24] 
-  * Min. SIZE (0x01) = 16MB; max. SIZE (0xFF) = 4GB 
-  * SIZE is a mask; only 8 legal values (0x01, 0x03, 0x07, 0x0F, etc.) 
-== Register Window == 
-  * Fixed SIZE of 1MB 
-  * BASE register 
-== Configurable Windows == 
-  * 16-bit BASE & SIZE registers 
-  * BASE corresponds to address bits [31:16] 
-  * Min. SIZE (0x0001) = 64KB; max. SIZE (0xFFFF) = 4GB 
-  * SIZE is a mask; 16 legal values 
-=== SATA Address Decoding === 
-  * 4x address windows 
-  * SDRAM and PCIe interface access 
-=== GbE Address Decoding === 
-  * 6x address windows 
-  * SDRAM interface access only 
-=== USB Address Decoding === 
-  * 4x address windows per USB port 
-  * SDRAM interface access only 
-=== SDIO Address Decoding === 
-  * 4x programmable address windows 
-  * SDRAM and PCIe interface access 
-=== Default Address Map === 
- 
-|DRAM CS0|256MB|0x00000000 - 0x0FFFFFFF| 
-|DRAM CS1|256MB|0x10000000 - 0x1FFFFFFF| 
-|DRAM CS2|256MB|0x20000000 - 0x2FFFFFFF| 
-|DRAM CS3|256MB|0x30000000 - 0x3FFFFFFF| 
-|reserved| |0x40000000 - 0x7FFFFFFF| 
-|PCIe Memory|512MB|0x80000000 - 0x9FFFFFFF| 
-|reserved| |0xA0000000 - 0xBFFFFFFF| 
-|PCIe I/O|64KB|0xC0000000 - 0xC000FFFF| 
-|reserved| |0xC0010000 - 0xC001FFFF| 
-|reserved| |0xC0020000 - 0xC800FFFF| 
-|Security SRAM|64KB (2KB)|0xC8010000 - 0xC801FFFF| 
-|reserved| |0xC8020000 - CFFFFFFF| 
-|Internal Registers|1MB|0xD0000000 - D00FFFFF| 
-|reserved| |0xD0100000 - 0xD7FFFFFF| 
-|NAND Flash|128MB|0xD8000000 - 0xDFFFFFFF| 
-|reserved| |0xE0000000 - 0xE7FFFFFF| 
-|SPI Flash|128MB|0xE8000000 - 0xEFFFFFFF| 
-|BootROM|128MB|0xF0000000 - 0xF7FFFFFF| 
-|Boot device|128MB|0xF8000000 - 0xFFFFFFFF| 
- 
- 
-RAM: 0x00000000 - 0x0FFFFFFF (256MB) 
  
 === EEPROM Data === === EEPROM Data ===
Line 497: Line 442:
 008003f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................ 008003f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
 </code> </code>
 +
 +==== Functional Specs ====
 +
 +=== CPU Address Decoding ===
 +Sheeva CPU core has 13 address windows:
 +  * 4x for CPU access to DRAM CS
 +  * 1x for CPU access to internal registers
 +  * 8x configurable for CPU access to remaining chip resources
 +== DRAM Windows ==
 +  * 8-bit BASE & SIZE registers
 +  * BASE corresponds to address bits [31:24]
 +  * Min. SIZE (0x01) = 16MB; max. SIZE (0xFF) = 4GB
 +  * SIZE is a mask; only 8 legal values (0x01, 0x03, 0x07, 0x0F, etc.)
 +== Register Window ==
 +  * Fixed SIZE of 1MB
 +  * BASE register
 +== Configurable Windows ==
 +  * 16-bit BASE & SIZE registers
 +  * BASE corresponds to address bits [31:16]
 +  * Min. SIZE (0x0001) = 64KB; max. SIZE (0xFFFF) = 4GB
 +  * SIZE is a mask; 16 legal values
 +=== SATA Address Decoding ===
 +  * 4x address windows
 +  * SDRAM and PCIe interface access
 +=== GbE Address Decoding ===
 +  * 6x address windows
 +  * SDRAM interface access only
 +=== USB Address Decoding ===
 +  * 4x address windows per USB port
 +  * SDRAM interface access only
 +=== SDIO Address Decoding ===
 +  * 4x programmable address windows
 +  * SDRAM and PCIe interface access
 +=== Default Address Map (p.41) ===
 +^Desc ^Size ^Base ^End ^Num ^State ^
 +|SDRAM CS0|256MB|0x0000 0000|0x0FFF FFFF| | |
 +|SDRAM CS1|256MB|0x1000 0000|0x1FFF FFFF| | |
 +|SDRAM CS2|256MB|0x2000 0000|0x2FFF FFFF| | |
 +|SDRAM CS3|256MB|0x3000 0000|0x3FFF FFFF| | |
 +|reserved| |0x4000 0000|0x7FFF FFFF| | |
 +|PCIe Memory|512MB|0x8000 0000|0x9FFF FFFF| | |
 +|PCIe-1 Memory|512MB|0xA000 0000|0xBFFF FFFF|(reserved)|6282 guess|
 +|PCIe I/O|64KB|0xC000 0000|0xC000 FFFF| | |
 +|PCIe-1 I/O|64KB|0xC001 0000|0xC001 FFFF|(reserved)|6282 guess|
 +|reserved| |0xC002 0000|0xC800 FFFF| | |
 +|Security SRAM|64KB (2KB)|0xC801 0000|0xC801 FFFF| | |
 +|reserved| |0xC802 0000|0xCFFF FFFF| | |
 +|Internal Registers|1MB|0xD000 0000|0xD00F FFFF| | |
 +|reserved| |0xD010 0000|0xD7FF FFFF| | |
 +|NAND Flash|128MB|0xD800 0000|0xDFFF FFFF| | |
 +|reserved| |0xE000 0000|0xE7FF FFFF| | |
 +|SPI Flash|128MB|0xE800 0000|0xEFFF FFFF| | |
 +|BootROM|128MB|0xF000 0000|0xF7FF FFFF| | |
 +|Boot device|128MB|0xF800 0000|0xFFFF FFFF| | |
 +=== LaCie Configured Address Map (mvSysHwConfig.h) ===
 +^Desc ^Size ^Base ^Notes ^Num ^State ^
 +|SDRAM CS0|256MB|0x00000000| | |dis|
 +|SDRAM CS1|256MB|0x10000000| | |dis|
 +|SDRAM CS2|256MB|0x20000000| | |dis|
 +|SDRAM CS3|256MB|0x30000000| | |dis|
 +|PEX0 MEM|128M|0x90000000| |0|en|
 +|PEX1 MEM|128M|0x98000000|6282 only|1|en|
 +|PEX0 I/O|16M|0xF0000000| |2|en|
 +|INTER REGS|1M?|0xF1000000| |8|en|
 +|PEX1 I/O|16M|0xF2000000|6282 only|3|en|
 +|DEVICE CS2|1M|0xF4000000|Boot ROM|9|dis|
 +|DEVICE CS1|16M|0xF8000000|SPI|5|en|
 +|DEVICE CS0|8M|0xF9000000|NAND|4|en|
 +|CRYPT ENG|64K|0xFB000000| |7|en|
 +|DEVICE CS3|16M|0xFF000000|Boot device|0xA|dis|
 +
 +Wish I found this earlier (kirkwood/cpu.c): Linux expects the internal registers to be at 0xF1000000
 +
 +Internal registers base address is set in register offset 0x20080 (arch-kirkwood/kirkwood.h): i.e. 0xF1020080 = 0xF1000000
 +
2big_nas.1371130288.txt.gz ยท Last modified: 2013/06/13 15:31 by hanno