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2big_nas [2013/06/12 15:05] – hanno | 2big_nas [2013/07/04 07:57] (current) – hanno | ||
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^Func ^Designator ^Description ^Part ^Notes | ^Func ^Designator ^Description ^Part ^Notes | ||
- | |CPU|IC23|Marvell Kirkwood 88F6282|88F6282A1C200|| | + | |CPU|IC23|Marvell Kirkwood 88F6282|[[http:// |
- | |ROM|IC15|4Gb (512Mx8) NAND Flash|HY27UF084G2B-TPCB|| | + | |ROM|IC15|4Gb (512Mx8) NAND Flash|[[http:// |
- | |RAM|IC4, | + | |RAM|IC4, |
||||| | ||||| | ||
- | |RTC|IC28? | + | |RTC|IC28? |
- | |NIC|IC3|Marvell Alaska 88E1518 GbE transceiver|88E1518-NNB2|| | + | |NIC|IC3|Marvell Alaska 88E1518 GbE transceiver|[[http:// |
- | |eSATA|IC16|JMicron JMB360 PCIe to SATA II Host Controller|JMB360|| | + | |eSATA|IC16|JMicron JMB360 PCIe to SATA II Host Controller|[[http:// |
||||| | ||||| | ||
- | |PLD|IC24|Altera MAX EPM3064A PLD|EPM3064ATC100-7N / EPM3064ATI100-10N|| | + | |PLD|IC24|Altera MAX EPM3064A PLD|[[http:// |
- | |E2|IC2|8Kb (1Kx8) I< | + | |E2|IC2|8Kb (1Kx8) I< |
||||| | ||||| | ||
- | |REG|IC17, | + | |REG|IC17, |
- | |REG|IC22|Marvell 88PG847B 4.5A Current-Limited Buck Regulator, 1MHz|88PG847B|| | + | |REG|IC22|Marvell 88PG847B 4.5A Current-Limited Buck Regulator, 1MHz|[[http:// |
- | |REG|IC34|TI TPS51100 3A DDR Termination Regulator|TPS51100|| | + | |REG|IC34|TI TPS51100 3A DDR Termination Regulator|[[http:// |
===== Headers ===== | ===== Headers ===== | ||
Line 382: | Line 382: | ||
==== Toolchain ==== | ==== Toolchain ==== | ||
- | * The Ubuntu 12.04.2 LTS ARM toolchain (arm-linux-gnueabi) is broken for this target. A U-Boot image will successfully compile but will not boot. The LaCie GPL U-Boot source will not compile at all (processor Thumb support error). | + | * The Ubuntu 12.04.2 LTS version of the arm-linux-gnueabi |
+ | * The Ubuntu 13.04 version of the same toolchain works. | ||
+ | |||
+ | ==== Discoveries ==== | ||
+ | |||
+ | === I2C Devices === | ||
+ | |||
+ | < | ||
+ | 2bigNAS> i2c probe | ||
+ | Valid chip addresses: 3E 50 51 52 53 64 68 | ||
+ | </ | ||
+ | |||
+ | ^Address ^Part ^Description ^ | ||
+ | |0x3E|G762|Fan controller| | ||
+ | |0x50 - 0x53|HT24LC08|1KB EEPROM| | ||
+ | |0x64|Debug Port/Serial ROM ?|| | ||
+ | |0x68|DS1337|RTC| | ||
+ | |||
+ | === EEPROM Data === | ||
+ | |||
+ | ^Offset ^Size ^Value ^Description ^ | ||
+ | |0x000|1|0x00| | | ||
+ | |0x001|1|0x04|EEPROM version| | ||
+ | |0x002|6|unique|MAC address; big endian| | ||
+ | |0x008|6 ?|0xFF| | | ||
+ | |0x00E|1 ?|0x01| | | ||
+ | |0x00F|74 ? | ||
+ | |0x0C5|1 ? | ||
+ | |Remainder||0xFF| | | ||
+ | |||
+ | < | ||
+ | 2bigNAS> i2c read 0x50 0x0 0x100 0x800000 | ||
+ | 2bigNAS> i2c read 0x51 0x0 0x100 0x800100 | ||
+ | 2bigNAS> i2c read 0x52 0x0 0x100 0x800200 | ||
+ | 2bigNAS> i2c read 0x53 0x0 0x100 0x800300 | ||
+ | 2bigNAS> md.b 0x800000 0x400 | ||
+ | 00800000: 00 04 My MA CA dd re ss ff ff ff ff ff ff 01 53 ...............S | ||
+ | 00800010: 6c 65 65 70 20 6d 6f 64 65 20 64 69 73 61 62 6c leep mode disabl | ||
+ | 00800020: 65 64 0a 53 65 74 20 6c 65 64 20 6d 6f 64 65 3a ed.Set led mode: | ||
+ | 00800030: 20 73 79 73 74 65 6d 5f 6f 66 66 0a 53 65 74 20 | ||
+ | 00800040: 6c 65 64 20 6d 6f 64 65 3a 20 73 79 73 74 65 6d led mode: system | ||
+ | 00800050: 5f 73 74 61 72 74 75 70 0a ff ff ff ff ff ff ff _startup........ | ||
+ | 00800060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 00800070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 00800080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 00800090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 008000a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 008000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 008000c0: ff ff ff ff ff 01 ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 008000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 008000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 008000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | : | ||
+ | : | ||
+ | : | ||
+ | 008003c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 008003d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 008003e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | 008003f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ | ||
+ | </ | ||
+ | |||
+ | ==== Functional Specs ==== | ||
+ | |||
+ | === CPU Address Decoding === | ||
+ | Sheeva CPU core has 13 address windows: | ||
+ | * 4x for CPU access to DRAM CS | ||
+ | * 1x for CPU access to internal registers | ||
+ | * 8x configurable for CPU access to remaining chip resources | ||
+ | == DRAM Windows == | ||
+ | * 8-bit BASE & SIZE registers | ||
+ | * BASE corresponds to address bits [31:24] | ||
+ | * Min. SIZE (0x01) = 16MB; max. SIZE (0xFF) = 4GB | ||
+ | * SIZE is a mask; only 8 legal values (0x01, 0x03, 0x07, 0x0F, etc.) | ||
+ | == Register Window == | ||
+ | * Fixed SIZE of 1MB | ||
+ | * BASE register | ||
+ | == Configurable Windows == | ||
+ | * 16-bit BASE & SIZE registers | ||
+ | * BASE corresponds to address bits [31:16] | ||
+ | * Min. SIZE (0x0001) = 64KB; max. SIZE (0xFFFF) = 4GB | ||
+ | * SIZE is a mask; 16 legal values | ||
+ | === SATA Address Decoding === | ||
+ | * 4x address windows | ||
+ | * SDRAM and PCIe interface access | ||
+ | === GbE Address Decoding === | ||
+ | * 6x address windows | ||
+ | * SDRAM interface access only | ||
+ | === USB Address Decoding === | ||
+ | * 4x address windows per USB port | ||
+ | * SDRAM interface access only | ||
+ | === SDIO Address Decoding === | ||
+ | * 4x programmable address windows | ||
+ | * SDRAM and PCIe interface access | ||
+ | === Default Address Map (p.41) === | ||
+ | ^Desc ^Size ^Base ^End ^Num ^State ^ | ||
+ | |SDRAM CS0|256MB|0x0000 0000|0x0FFF FFFF| | | | ||
+ | |SDRAM CS1|256MB|0x1000 0000|0x1FFF FFFF| | | | ||
+ | |SDRAM CS2|256MB|0x2000 0000|0x2FFF FFFF| | | | ||
+ | |SDRAM CS3|256MB|0x3000 0000|0x3FFF FFFF| | | | ||
+ | |reserved| |0x4000 0000|0x7FFF FFFF| | | | ||
+ | |PCIe Memory|512MB|0x8000 0000|0x9FFF FFFF| | | | ||
+ | |PCIe-1 Memory|512MB|0xA000 0000|0xBFFF FFFF|(reserved)|6282 guess| | ||
+ | |PCIe I/ | ||
+ | |PCIe-1 I/ | ||
+ | |reserved| |0xC002 0000|0xC800 FFFF| | | | ||
+ | |Security SRAM|64KB (2KB)|0xC801 0000|0xC801 FFFF| | | | ||
+ | |reserved| |0xC802 0000|0xCFFF FFFF| | | | ||
+ | |Internal Registers|1MB|0xD000 0000|0xD00F FFFF| | | | ||
+ | |reserved| |0xD010 0000|0xD7FF FFFF| | | | ||
+ | |NAND Flash|128MB|0xD800 0000|0xDFFF FFFF| | | | ||
+ | |reserved| |0xE000 0000|0xE7FF FFFF| | | | ||
+ | |SPI Flash|128MB|0xE800 0000|0xEFFF FFFF| | | | ||
+ | |BootROM|128MB|0xF000 0000|0xF7FF FFFF| | | | ||
+ | |Boot device|128MB|0xF800 0000|0xFFFF FFFF| | | | ||
+ | === LaCie Configured Address Map (mvSysHwConfig.h) === | ||
+ | ^Desc ^Size ^Base ^Notes ^Num ^State ^ | ||
+ | |SDRAM CS0|256MB|0x00000000| | |dis| | ||
+ | |SDRAM CS1|256MB|0x10000000| | |dis| | ||
+ | |SDRAM CS2|256MB|0x20000000| | |dis| | ||
+ | |SDRAM CS3|256MB|0x30000000| | |dis| | ||
+ | |PEX0 MEM|128M|0x90000000| |0|en| | ||
+ | |PEX1 MEM|128M|0x98000000|6282 only|1|en| | ||
+ | |PEX0 I/ | ||
+ | |INTER REGS|1M? | ||
+ | |PEX1 I/ | ||
+ | |DEVICE CS2|1M|0xF4000000|Boot ROM|9|dis| | ||
+ | |DEVICE CS1|16M|0xF8000000|SPI|5|en| | ||
+ | |DEVICE CS0|8M|0xF9000000|NAND|4|en| | ||
+ | |CRYPT ENG|64K|0xFB000000| |7|en| | ||
+ | |DEVICE CS3|16M|0xFF000000|Boot device|0xA|dis| | ||
+ | |||
+ | Wish I found this earlier (kirkwood/ | ||
+ | |||
+ | Internal registers base address is set in register offset 0x20080 (arch-kirkwood/ |