2big_nas
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| 2big_nas [2013/06/27 09:40] – hanno | 2big_nas [2013/07/04 07:57] (current) – hanno | ||
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| Line 475: | Line 475: | ||
| * 4x programmable address windows | * 4x programmable address windows | ||
| * SDRAM and PCIe interface access | * SDRAM and PCIe interface access | ||
| - | === Default Address Map === | + | === Default Address Map (p.41) === |
| + | ^Desc ^Size ^Base ^End ^Num ^State ^ | ||
| + | |SDRAM CS0|256MB|0x0000 0000|0x0FFF FFFF| | | | ||
| + | |SDRAM CS1|256MB|0x1000 0000|0x1FFF FFFF| | | | ||
| + | |SDRAM CS2|256MB|0x2000 0000|0x2FFF FFFF| | | | ||
| + | |SDRAM CS3|256MB|0x3000 0000|0x3FFF FFFF| | | | ||
| + | |reserved| |0x4000 0000|0x7FFF FFFF| | | | ||
| + | |PCIe Memory|512MB|0x8000 0000|0x9FFF FFFF| | | | ||
| + | |PCIe-1 Memory|512MB|0xA000 0000|0xBFFF FFFF|(reserved)|6282 guess| | ||
| + | |PCIe I/ | ||
| + | |PCIe-1 I/ | ||
| + | |reserved| |0xC002 0000|0xC800 FFFF| | | | ||
| + | |Security SRAM|64KB (2KB)|0xC801 0000|0xC801 FFFF| | | | ||
| + | |reserved| |0xC802 0000|0xCFFF FFFF| | | | ||
| + | |Internal Registers|1MB|0xD000 0000|0xD00F FFFF| | | | ||
| + | |reserved| |0xD010 0000|0xD7FF FFFF| | | | ||
| + | |NAND Flash|128MB|0xD800 0000|0xDFFF FFFF| | | | ||
| + | |reserved| |0xE000 0000|0xE7FF FFFF| | | | ||
| + | |SPI Flash|128MB|0xE800 0000|0xEFFF FFFF| | | | ||
| + | |BootROM|128MB|0xF000 0000|0xF7FF FFFF| | | | ||
| + | |Boot device|128MB|0xF800 0000|0xFFFF FFFF| | | | ||
| + | === LaCie Configured Address Map (mvSysHwConfig.h) | ||
| ^Desc ^Size ^Base ^Notes ^Num ^State ^ | ^Desc ^Size ^Base ^Notes ^Num ^State ^ | ||
| |SDRAM CS0|256MB|0x00000000| | |dis| | |SDRAM CS0|256MB|0x00000000| | |dis| | ||
| Line 492: | Line 513: | ||
| |DEVICE CS3|16M|0xFF000000|Boot device|0xA|dis| | |DEVICE CS3|16M|0xFF000000|Boot device|0xA|dis| | ||
| - | * from func. spec. * | + | Wish I found this earlier (kirkwood/cpu.c): Linux expects the internal registers to be at 0xF1000000 |
| - | |reserved| |0xA0000000 - 0xBFFFFFFF| | + | |
| - | |PCIe I/O|64KB|0xC0000000 - 0xC000FFFF| | + | Internal |
| - | |reserved| |0xC0010000 - 0xC001FFFF| | + | |
| - | |reserved| |0xC0020000 - 0xC800FFFF| | + | |
| - | |Security SRAM|64KB (2KB)|0xC8010000 - 0xC801FFFF| | + | |
| - | |reserved| |0xC8020000 - 0xCFFFFFFF| | + | |
| - | |Internal | + | |
| - | |reserved| |0xD0100000 - 0xD7FFFFFF| | + | |
| - | |NAND Flash|128MB|0xD8000000 - 0xDFFFFFFF| | + | |
| - | |reserved| |0xE0000000 - 0xE7FFFFFF| | + | |
| - | |SPI Flash|128MB|0xE8000000 - 0xEFFFFFFF| | + | |
| - | |BootROM|128MB|0xF0000000 - 0xF7FFFFFF| | + | |
| - | |Boot device|128MB|0xF8000000 - 0xFFFFFFFF| | + | |
| - | Bloody hell... | ||
| - | * # | ||
| - | * #define INTER_REGS_BASE | ||
| - | * #define NAND_FLASH_BASE | ||
| - | * #define BOOTER_PAGE_NUM | ||
| - | * #define BOOTER_BASE | ||
| - | * #define BOOTER_END | ||
| - | * #define NAND_CMD_PORT | ||
| - | * #define NAND_ADDR_PORT | ||
| - | * #define NUM_BLOCKS | ||
| - | * #define PAGES_PER_BLOCK | ||
| - | * #define PAGE_SIZE | ||
| - | * #define SPARE_SIZE | ||
| - | * #define CFG_NAND_PAGE_SIZE | ||
| - | * #define CFG_NAND_BLOCK_SIZE | ||
| - | * #define CFG_NAND_PAGE_COUNT | ||
| - | * #define CFG_NAND_BAD_BLOCK_POS | ||
| - | * #define CFG_NAND_U_BOOT_OFFS | ||
| - | * #define CFG_NAND_U_BOOT_SIZE | ||
| - | * #define CFG_NAND_U_BOOT_DST | ||
| - | * #define CFG_NAND_U_BOOT_START | ||
| - | * | ||
2big_nas.txt · Last modified: 2013/07/04 07:57 by hanno
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